Efficient parallel cyclic redundancy check calculation using modulo-2 multiplications

ABSTRACT

A system and method for cyclic redundancy checks (CRC) having a CRC polynomial of width (W) for use in a digital signal processing system is disclosed. The system includes receiving a message ({right arrow over (m)}) and decomposing that message ({right arrow over (m)}) into a series of smaller blocks ({right arrow over (b)} i ). Each block ({right arrow over (b)} i ) is of size (M) and is related to a unit vector ({right arrow over (e)} i ). A summation operation on the blocks ({right arrow over (b)} i ) given by CRC({right arrow over (b)})=Σb i ·CRC({right arrow over (e)} i ) is performed. Each CRC of the unit vectors (CRC({right arrow over (e)} i )) is stored in a lookup table. The lookup table is tagged by the “one” bits of the message block. An exclusive OR (XOR) operation is performed on each tagged row of the lookup table to calculate the CRC of the message.

TECHNICAL FIELD OF THE INVENTION

The present invention relates generally to data processing systems and,more specifically, to constructs and methods for optimizing efficiencyand capacity of cyclic redundancy check operations.

BACKGROUND OF THE INVENTION

In current systems, parallel cyclic redundancy check (CRC) computationsinvolve decomposing an N-bit message into small blocks. Each block has afixed size (M). The fixed size typically equals the polynomial degree.Most approaches include computing the CRC of a message and performing aseries of N/M Galois multiply-accumulate operations. Each of the N/Mblocks is multiplied by a pre-stored coefficient, divided by the CRCpolynomial, and added to the accumulator. Accordingly, these systemsrequire N/M Galois parallel multiply-accumulate operations.

There are a number of disadvantages to such approaches. For example,Galois multipliers typically require the use of special hardware with aconsiderable number of logical gates. Conventional Galois multiplierarchitectures consume large areas of silicon. Moreover, Galoisoperations are rarely used in common applications. Furthermore, the CRCploynomial is typically hardwired into an efficient Galois multiplier.Such a design is not reconfigurable to support other polynomials.

There is therefore a need for a system and method that provides aparallel algorithm that uses a mathematical operation, which requires nospecial logic and is configurable to any polynomial.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure include a cyclic redundancy check(CRC) system for CRC calculations of small message blocks via a lookuptable-based parallel algorithm.

In one embodiment, a method for cyclic redundancy checks (CRC) having aCRC polynomial of width (W) is disclosed. The method includes receivinga message ({right arrow over (m)}). The method also includes decomposingthe message ({right arrow over (m)}) into a series of smaller blocks({right arrow over (b)}_(i)) of size (M) and unit vectors ({right arrowover (e)}_(i)). The method further includes performing a summationoperation on the blocks ({right arrow over (b)}_(i)) given by

${{{CRC}\text{(}\overset{->}{b}\text{)}} = {\sum{{b_{i} \cdot {CRC}}\text{(}{\overset{->}{e}}_{i}\text{)}}}},$

wherein the CRC of the unit vectors (CRC({right arrow over (e)}_(i))) isstored in a lookup table.

In another embodiment, a system for cyclic redundancy checks (CRC)having a CRC polynomial of width (W) is disclosed. The system includes acontroller capable of receiving a message ({right arrow over (m)}) anddecomposing the message ({right arrow over (m)}) into a series ofsmaller blocks ({right arrow over (b)}_(i)) of size (M) and unit vectors({right arrow over (e)}_(i)). The controller is further capable ofperforming a summation operation on the blocks ({right arrow over(b)}_(i)) given by

${{{CRC}\text{(}\overset{->}{b}\text{)}} = {\sum{{b_{i} \cdot {CRC}}\text{(}{\overset{->}{e}}_{i}\text{)}}}},$

wherein the CRC of the unit vectors (CRC({right arrow over (e)}_(i))) isstored in a lookup table.

In still another embodiment, a process for cyclic redundancy checks(CRC) for use in a signal processing system is disclosed. The processincludes decomposing a message ({right arrow over (m)}) into a series ofsmaller blocks ({right arrow over (b)}_(i)) of size (M) and unit vectors({right arrow over (e)}_(i)). The process also includes performing asummation operation on the blocks ({right arrow over (b)}_(i)), whereinthe operation is given by

${{CRC}\text{(}\overset{->}{b}\text{)}} = {\sum{{b_{i} \cdot {CRC}}\text{(}{\overset{->}{e}}_{i}{\text{)}.}}}$

Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, itmay be advantageous to set forth definitions of certain words andphrases used throughout this patent document: the terms “include” and“comprise,” as well as derivatives thereof, mean inclusion withoutlimitation; the term “or,” is inclusive, meaning and/or; the phrases“associated with” and “associated therewith,” as well as derivativesthereof, may mean to include, be included within, interconnect with,contain, be contained within, connect to or with, couple to or with, becommunicable with, cooperate with, interleave, juxtapose, be proximateto, be bound to or with, have, have a property of, or the like; and theterms “element”, “construct” or “component” may mean any device, systemor part thereof that performs a processing, control or communicationoperation; and such a device may be implemented in hardware, firmware orsoftware, or some combination of at least two of the same. It should benoted that the functionality associated with any particular construct orcomponent may be centralized or distributed, whether locally orremotely. Definitions for certain words and phrases are providedthroughout this patent document, those of ordinary skill in the artshould understand that in many, if not most instances, such definitionsapply to prior, as well as future uses of such defined words andphrases.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure and itsadvantages, reference is now made to the following description taken inconjunction with the accompanying drawings, in which like referencenumerals represent like parts:

FIG. 1 illustrates a simplified block diagram of an exemplary digitalsignal processing system and controller for cyclic redundancy check(CRC) calculations according to one embodiment of the presentdisclosure;

FIG. 2 illustrates a lookup table for CRC calculations according to oneembodiment of the present disclosure;

FIG. 3 illustrates a tree-wise summation of table entries according toone embodiment of the present disclosure;

FIG. 4 illustrates a lookup table and tags for CRC calculation accordingto one embodiment of the present disclosure; and

FIG. 5 is simplified flowchart illustrating a method in accordance withone embodiment of the present disclosure.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 1 through 5, discussed below, and the various embodiments used todescribe the principles of the present disclosure in this patentdocument are by way of illustration only, and should not be construed inany way to limit the scope of the disclosure. Hereinafter, certainaspects of the present disclosure are described in relation toillustrative embodiments and operations of wireless communicationssystems and networks. Those skilled in the art, however, will understandthat the principles and teachings of the present disclosure may beimplemented in a variety of suitably arranged signal processing systemsutilized in any number of end-equipment applications.

FIG. 1 a simplified block diagram of a system 100 for cyclic redundancycheck calculations in accordance with one embodiment of the presentdisclosure. System 100 includes a digital signal processing system 101having an input 102 and an output 103. By way of example, system 100 mayinclude wire line or wireless communication devices (including cellphones, PCS handsets, personal digital assistant (PDA) handsets,portable computers, telemetry devices, etc.), computer systems, audioand video equipment, satellite communications, multimedia applications,home automation systems and any other systems requiring digital signalprocessing. Digital signal processing system 101 includes a controller104 for performing cyclic redundancy check calculations according to oneembodiment of the present disclosure. Digital signal processing system101 includes a lookup table 106. It should be understood thatembodiments of the present disclosure may implemented into existingequipment, such as multipliers.

Typical Galois multiply-accumulate systems include a message ({rightarrow over (m)}) consisting of N bits. The message is a superposition ofa plurality of blocks ({right arrow over (b)}_(i)). Each block ({rightarrow over (b)}_(i)) is of a fixed size (e.g., M bits). The blocks aremultiplied over a Galois Field of prime two (e.g., GF(2)) with unitvectors ({right arrow over (e)}_(i)) shifted by M bits with respect toeach other. Thus, the message ({right arrow over (m)}) can be decomposedas shown by Equation 1 below.

$\begin{matrix}{\overset{->}{m} = {\sum\limits_{i = 0}^{{N/M} - 1}{{\overset{->}{b}}_{i} \otimes {\overset{->}{e}}_{i}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 1} \right\rbrack\end{matrix}$

The summation and the multiplication operations included in Equation 1are performed over GF(2). The GF(2) multiplication is shown as thesymbol

while the GF(2) addition operation (an XOR operation) is shown as thesymbol “⊕”.

As an example of a typical application for Galois multiply-accumulatesystem, suppose a message ({right arrow over (m)}) containing sixteenbits (N=16) required decomposition and is equal to the binary sequence[110111100111010]. Suppose further that message ({right arrow over (m)})is a superposition of blocks ({right arrow over (b)}_(i)) of a fixednumber of bits (M). For example, suppose M=4 and the polynomial degree(or CRC width) W=3. Finally, suppose that the CRC polynomial ({rightarrow over (p)}) is equal to [1010] .

In typical Galois applications, message ({right arrow over (m)}) isfirst divided into four blocks [{right arrow over (b)}₀ {right arrowover (b)}₁ {right arrow over (b)}₂ {right arrow over (b)}₃] of four bitseach, where {right arrow over (b)}₀=1010, {right arrow over (b)}₁=0011,{right arrow over (b)}₂=1111 and {right arrow over (b)}₃=1101. Moreover,message ({right arrow over (m)}) is the superposition of the blocks({right arrow over (b)}_(i)) multiplied by unit vectors ({right arrowover (e)}_(i)) as given by Equation 2 below.

{right arrow over (m)}={right arrow over (b)}₀

{right arrow over (e)}₀⊕{right arrow over (b)}₁

{right arrow over (e)}₁⊕{right arrow over (b)}₂

{right arrow over (e)}₂⊕{right arrow over (b)}₃

{right arrow over (e)}₃   [Eqn. 2]

Continuing with the example above, suppose that the unit vectors ({rightarrow over (e)}_(i)) are given by {right arrow over (e)}₀=1, {rightarrow over (e)}₁=10000, {right arrow over (e)}₂=100000000 and {rightarrow over (e)}₃=1000000000000. Next, the CRC of the message ({rightarrow over (m)}) is given by the modulo-2 division of message ({rightarrow over (m)}) by the CRC polynomial ({right arrow over (p)}) as seenin Equation 3 below.

$\begin{matrix}\begin{matrix}{{{CRC}\text{(}\overset{->}{m}\text{)}} = {{CRC}\left( {\sum\limits_{i}{{\overset{->}{b}}_{i} \otimes {\overset{->}{e}}_{i}}} \right)}} \\{= {\sum\limits_{i}{{CRC}\text{(}{{\overset{->}{b}}_{i} \otimes \text{(}}{\overset{->}{e}}_{i}\text{)}\text{)}}}} \\{= {{CRC}\left( {\sum\limits_{i}{{CRC}\text{(}{\overset{->}{b}}_{i}{\text{)} \otimes {CRC}}\text{(}{\overset{->}{e}}_{i}\text{)}}} \right)}}\end{matrix} & \left\lbrack {{Eqn}.\mspace{14mu} 3} \right\rbrack\end{matrix}$

Using the modulation properties of Equations 4 and 5 below and afterassuming that x smaller than p (i.e., mod(x)_(p)=x), Equation 3 may besimplified to Equation 6 below, where {right arrow over(β)}_(i)≡CRC({right arrow over (e)}_(i)) and {right arrow over (β)}_(i)is a set of pre-computed coefficients:

$\begin{matrix}{{{mod}\left( {x \oplus y} \right)}_{p} = {{{mod}(x)}_{p} \oplus {{mod}(y)}_{p}}} & \left\lbrack {{Eqn}.\mspace{14mu} 4} \right\rbrack \\{{{mod}\left( {x \otimes y} \right)}_{p} = {{mod}\left( {{{mod}(x)}_{p} \otimes {{mod}(y)}_{p}} \right)}_{p}} & \left\lbrack {{Eqn}.\mspace{14mu} 5} \right\rbrack \\{{{CRC}\text{(}\overset{->}{m}\text{)}} \equiv {\sum\limits_{i}{{CRC}\text{(}{{\overset{->}{b}}_{i} \otimes {\overset{->}{\beta}}_{i}}\text{)}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 6} \right\rbrack\end{matrix}$

Expanding the summation in Equation 6 for a polynomial degree of W=3,Equation 7 results.

CRC({right arrow over (m)})=CRC(CRC({right arrow over (b)}₀)

β₀⊕CRC({right arrow over (b)}₁)

β₁βCRC({right arrow over (b)}₂)

β₂⊕CRC({right arrow over (b)}₃)

β₃)   [Eqn. 7]

Using the unit vectors ({right arrow over (e)}_(i)) defined earlier, theset of pre-computed coefficients ({right arrow over (β)}_(i)) may bederived as: {right arrow over (β)}_(i)=CRC(1)=001, {right arrow over(β)}_(i)=CRC(10000)=100, {right arrow over (β)}₂=CRC(100000000)=100 and{right arrow over (β)}₃=CRC(1000000000000)=100. In addition, the CRCs ofeach of the message blocks ({right arrow over (b)}_(i)) yield:CRC({right arrow over (b )}_(i))=000, CRC({right arrow over (b)}₁)=011,CRC({right arrow over (b )}₂)=101 and CRC({right arrow over (b)}₃)=111.Finally, the sum of the two GF(2) products is given by Equation 8.

$\begin{matrix}\begin{matrix}{{{CRC}\text{(}{\overset{->}{b}}_{0}{\text{)} \otimes {\overset{->}{\beta}}_{0}}} =} & 00000 \\{{{CRC}\text{(}{\overset{->}{b}}_{1}{\text{)} \otimes {\overset{->}{\beta}}_{1}}} =} & 01100 \\{{{CRC}\text{(}{\overset{->}{b}}_{2}{\text{)} \otimes {\overset{->}{\beta}}_{2}}} =} & 10100 \\{{{CRC}\text{(}{\overset{->}{b}}_{3}{\text{)} \otimes {\overset{->}{\beta}}_{3}}} =} & 11100 \\{\sum =} & 00100\end{matrix} & \left\lbrack {{Eqn}.\mspace{14mu} 8} \right\rbrack\end{matrix}$

Equation 8 yields the CRC of the message or CRC(00100)=100. Thus,according to one embodiment of the present disclosure a large message ofsize N may be parsed into a series of smaller blocks ({right arrow over(b)}_(i)) of size M and used to calculate the CRC of the message asgiven by Equation 3.

According to one embodiment of the present disclosure, to calculate theCRC of the message blocks (rather than the entire message), the blocks({right arrow over (b)}_(i)) are decomposed into M base vectors as givenby Equation 9.

$\begin{matrix}{\overset{->}{b} = {\sum\limits_{i = 0}^{M - 1}{b_{i} \cdot {\overset{->}{e}}_{i}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 9} \right\rbrack\end{matrix}$

It is noted that Equation 9 is a special case of Equation 1, where N=Mand M=1 (i.e., blocks ({right arrow over (b)}_(i)) are the block bits ofmessage ({right arrow over (m)})). Equation 9 also assumes that basevectors {right arrow over (e)}_(i) are shifted copies of each other andthat {right arrow over (b)}_(M-1)=1000 . . . 0. Finally, in accordancewith one embodiment of the present disclosure, the summation over GF(2)of the CRCs of the unit vectors are multiplied by their respectivecoefficients as given by Equation 10.

$\begin{matrix}{{{CRC}\text{(}\overset{->}{b}\text{)}} = {\sum{{b_{i} \cdot {CRC}}\text{(}{\overset{->}{e}}_{i}\text{)}}}} & \left\lbrack {{Eqn}.\mspace{14mu} 10} \right\rbrack\end{matrix}$

FIG. 2 is an exemplary lookup table 200 with rows 201. Lookup table 200stores the values of the CRC of the unit vectors (CRC({right arrow over(e)}_(i))) 202. Lookup table 200 is preferably an M×W matrix, where W isthe width of the CRC polynomial. Bits 202 of message block ({right arrowover (b)}_(i)) 202 act as tags for lookup table 200. In someembodiments, method 300 may be accomplished in a tree-wise fashion asshown in FIG. 3. In accordance with one embodiment of the presentdisclosure, XOR operations 302 between the selected table rows 301 maybe performed in a fully parallel fashion or in gradual steps. However,it should be understood that XOR operations 302 may be executed by anysuitable means.

Referring now to FIG. 4, table 400 includes multiple rows 401. Each row401 is populated with pre-stored CRC values 402. The CRC of the messageis generally a superposition of all CRC values 402 stored in table rows401 and tagged by a “1” bit 403. In other words, any row 401 tagged witha “1” bit 403 is subject to an XOR operation. As a specific example,suppose a message block {right arrow over (b)}=110111100111010, {rightarrow over (p)}=1010 and W=3. Using lookup table 400 in FIG. 4, rows 401tagged by the “1” bits 403 are summed together as shown in Equation 11.Equation 11 yields the same CRC message ({right arrow over (m)}),CRC({right arrow over (m)})=100, as found in Equation 8.

CRC({right arrow over (m)})=10⊕10⊕100⊕10 ⊕100 ⊕10 ⊕100 ⊕10 ⊕100 ⊕100 β10  [Eqn 11]

Accordingly, the CRC of a large message may be found using Equation 3 byusing a lookup table, performing multiplying-accumulating modulo-2(i.e., over GF(2)) with pre-stored coefficients ({right arrow over(β)}_(i) ) and finally dividing the accumulator by the CRC polynomial.The division by the CRC polynomial may be accomplished nibble-wise via alookup table of 16×W bits. Thus, according to one embodiment of thepresent disclosure, CRC calculations may be accomplished with a firstlookup table having M×W bits and a second lookup table having 16×W bitsfor the final CRC calculations. Each lookup table is preferably fullyreconfigurable. It should be understood that any suitable lookup tablemay be used in accordance with the present disclosure.

In one embodiment, there is no upper limit on the throughput (i.e., thenumber of XOR calculations performed in parallel. The estimated cyclecount for calculating the CRC of a message of size N is given byEquation 12, where K is the number of XOR calculation performed.

$\begin{matrix}{{{\frac{N}{M}\left( {{\log_{K}(M)} + 1} \right)} + \left\lfloor \frac{{2W} - 1}{4} \right\rfloor} \propto {\frac{N}{M}{\log_{K}(M)}}} & \left\lbrack {{Eqn}.\mspace{14mu} 12} \right\rbrack\end{matrix}$

If full pipelining is assumed, the term (log_(K)(M)+1) may be eliminatedfrom Equation 12. Thus, the CRC of a message block may be calculatedwithin a single clock cycle. Moreover, a system in accordance with oneembodiment of the present disclosure does not require specializedhardware, such as Galois multipliers. In the specific case of largermessage blocks, existing multiplier may be used in accordance with thepresent disclosure for the modulo-2 multiply-accumulate operations ifthe carry-bit capability is turned off.

FIG. 5 is a simplified flowchart illustrating method 500 according toone embodiment of the present disclosure. Method 500 includes cyclicredundancy checks (CRC) for use in various digital signal processingsystems. Method 500 begins with receiving a message ({right arrow over(m)}) in step 501 and decomposing that message ({right arrow over (m)})into a series of smaller blocks ({right arrow over (b)}_(i)) in step502. Each block ({right arrow over (b)}_(i)) is of size (M) and isrelated to a unit vector ({right arrow over (e)}_(i)). A summationoperation on the blocks ({right arrow over (b)}_(i)) given by

${{CRC}\text{(}\overset{->}{b}\text{)}} = {\sum{{b_{i} \cdot {CRC}}\text{(}{\overset{->}{e}}_{i}\text{)}}}$

performed in step 503, where each CRC of the unit vectors (CRC({rightarrow over (e)}_(i))) is found using a lookup table, such as lookuptable 400. The lookup table 400 is tagged by the “one” bits 402 of themessage block. An exclusive OR (XOR) operation is performed on eachtagged rows of lookup table 400 to calculate the CRC of the message instep 504. Finally, the CRC of the message is output in step 505.

It should be understood that embodiments of the present disclosure maybe implemented into existing designs without requiring special hardware.Although certain aspects of the present disclosure have been describedin relations to specific systems, standards and structures, it should beeasily appreciated by one of skill in the art that the system of thepresent disclosure provides and comprehends a wide array of variationsand combinations easily adapted to a number of signal processingsystems. As described herein, the relative arrangement and operation ofnecessary functions may be provided in any manner suitable for aparticular application. All such variations and modifications are herebycomprehended. It should also be appreciated that the constituent membersor components of this system may be produced or provided using anysuitable hardware, firmware, software, or combination(s) thereof.

The embodiments and examples set forth herein are therefore presented tobest explain the present disclosure and its practical application, andto thereby enable those skilled in the art to make and utilize thesystem of the present disclosure. The description as set forth herein istherefore not intended to be exhaustive or to limit any invention to aprecise form disclosed. As stated throughout, many modifications andvariations are possible in light of the above teaching without departingfrom the spirit and scope of the following claims.

1. A method for cyclic redundancy checks (CRC) having a CRC polynomialof width (W), comprising: receiving a message ({right arrow over (m)});decomposing the message ({right arrow over (m)}) into a series ofsmaller blocks ({right arrow over (b)}_(i)) of size (M) and unit vectors({right arrow over (e)}_(i)); and performing a summation operation onthe blocks ({right arrow over (b)}_(i)) given by${{{CRC}\text{(}\overset{->}{b}\text{)}} = {\sum{{b_{i} \cdot {CRC}}\text{(}{\overset{->}{e}}_{i}\text{)}}}},$wherein the CRC of the unit vectors (CRC({right arrow over (e)}_(i))) isstored in a lookup table.
 2. The method of claim 1 further comprising:tagging the lookup table with bits of the blocks ({right arrow over(b)}_(i)).
 3. The method of claim 2, wherein the bits are “one” bits. 4.The method of claim 2 further comprising: performing an exclusive OR(XOR) operation on tagged rows of the lookup table.
 5. The method ofclaim 4, wherein the XOR operation is conducted in parallel with anotherXOR operation.
 6. The method of claim 4, wherein the XOR operation isconducted in a tree-wise fashion.
 7. The method of claim 1, wherein thelookup table is M×W bits.
 8. The method of claim 1 further comprising:reconfiguring the CRC polynomial.
 9. The method of claim 8, wherein thereconfiguring is accomplished by loading a new lookup table for the CRCof the unit vectors ({right arrow over (e)}_(i)).
 10. A system forcyclic redundancy checks (CRC) having a CRC polynomial of width (W),comprising: a controller capable of: receiving a message ({right arrowover (m)}); decomposing the message ({right arrow over (m)}) into aseries of smaller blocks ({right arrow over (b)}_(i)) of size (M) andunit vectors ({right arrow over (e)}_(i)); and performing a summationoperation on the blocks ({right arrow over (b)}_(i)) given by${{{CRC}\text{(}\overset{->}{b}\text{)}} = {\sum{{b_{i} \cdot {CRC}}\text{(}{\overset{->}{e}}_{i}\text{)}}}},$wherein the CRC of the unit vectors (CRC({right arrow over (e)}_(i))) isstored in a lookup table.
 11. The system of claim 10, wherein bits ofthe blocks ({right arrow over (b)}_(i)) are a tag for the lookup table.12. The system of claim 11, wherein the bits are “one” bits.
 13. Thesystem of claim 11, wherein the tag indicates which rows of the lookuptable require an exclusive OR (XOR) operation.
 14. The system of claim13, wherein the XOR operation is conducted in parallel with another XORoperation.
 15. The system of claim 13, wherein the XOR operation isconducted in a tree-wise fashion.
 16. The system of claim 10, whereinthe lookup table is M×W bits.
 17. The system of claim 10, wherein theCRC polynomial is reconfigured by loading a new lookup table for the CRCof the unit vectors ({right arrow over (e)}_(i)).
 18. For use in asignal processing system, a process for cyclic redundancy checks (CRC),comprising: decomposing a message ({right arrow over (m)}) into a seriesof smaller blocks ({right arrow over (b)}_(i)) of size (M) and unitvectors ({right arrow over (e)}_(i)); and performing a summationoperation on the blocks ({right arrow over (b)}_(i)), wherein theoperation is given by${{CRC}\text{(}\overset{->}{b}\text{)}} = {\sum{{b_{i} \cdot {CRC}}\text{(}{\overset{->}{e}}_{i}{\text{)}.}}}$19. The process of claim 18 further comprising: looking up values forthe CRC of the unit vectors (CRC({right arrow over (e)}_(i))) in alookup table.
 20. The process of claim 18 further comprising: taggingthe lookup table with “one” bits of the blocks ({right arrow over(b)}_(i)).
 21. The process of claim 20 further comprising: performing anexclusive OR (XOR) operation on tagged rows of the lookup table.
 22. Theprocess of claim 21, wherein the XOR operation is conducted in parallelwith another XOR operation.
 23. The process of claim 21, wherein the XORoperation is conducted in a tree-wise fashion.
 24. The process of claim18, wherein the lookup table is M×W bits, wherein W is a width of a CRCpolynomial.
 25. The process of claim 18 further comprising:reconfiguring the CRC polynomial by loading a new lookup table for theCRC of the unit vectors ({right arrow over (e)}_(i)).